In eDRAM applications with a deep trench as capacitor, a buried plate (bottom electrode), dielectric and top electrode are needed to form a capacitor for the eDRAM to function. Typically the buried plate is formed by either doped silicon glass (phosphorus- or arsenic-doped silicon glass (ASG)) fill-and-out-diffusion process or ion implantation into the sidewall of deep trenches in a silicon substrate. eDRAM devices having a bottom electrode produced in this manner, however, can suffer from low conductivity issues that slow down eDRAM performance. Further, with eDRAM cell and deep trench scaling down, it is even more challenging to get enough dopant into the buried plate using doped silicon glass (ASG) or ion implantation to form a highly conductive bottom electrode due to the small trench (critical dimension) size and higher aspect ratio.
Therefore, scalable, eDRAM fabrication techniques that address the above-described problems would be desirable.